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alert on lan* asic networking silicon datasheet product features n full system management solution with environmental instrumentation n smb interface to host n multiple transmissions of all sos packets n five external maskable sos events n automatic heartbeat generation when system is powered-off n watchdog timer for detection of system hang n power plane signal detection for low power state status n clock synchronization and smooth transition logic n 82558 b-step fast ethernet** controller compliance only figure 1. alert on lan asic block diagram event interface smb inter- face tco interface eeprom inter- face clk sync miscellaneous logic 128 byte sync ram decode event timers packet control registers & data mux order number: 692818-003 version 1.2 july 1998
alert on lan* asic networking silicon ii datasheet revision history revision date version description oct. 1997 1.0 first release feb. 1998 1.1 general editing july 1998 1.2 expanded section 2.4, "event interface" to include more detail and added section 5.0, "reset and test modes" information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the alert on lan* asic may contain design defects or errors known as errata which may cause the product to deviate from publish ed specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copyright ? intel corporation, 1997 * alert on lan is a result of the intel-ibm advanced manageability alliance and a trademark of ibm. **third-party brands and names are the property of their respective owners.
datasheet iii networking silicon alert on lan* asic contents 1.0 introduction................................................................................................................ ..........1 1.1 alert on lan overview ....................................................................................................1 1.2 management overview ...................................................................................................1 1.3 alert on lan feature set ................................................................................................2 1.4 specifications and standards compliance...................................................................... 2 2.0 alert on lan asic architectural overview .............................................................3 2.1 tco interface............................................................................................................... ... 3 2.2 smb interface............................................................................................................... ... 5 2.3 eeprom interface ..........................................................................................................5 2.4 event interface ............................................................................................................. ... 6 2.4.1 new event definition and results ......................................................................6 2.4.2 external events ..................................................................................................7 2.4.3 event 1, sticky latch clearing mechanism ........................................................8 2.4.4 event 4, link detect and packet transmission interrupt.................................... 8 2.4.5 watchdog event .................................................................................................8 2.4.6 software event ...................................................................................................9 2.4.7 polarity functionality ..........................................................................................9 2.4.8 event status mask and smi mask .....................................................................9 2.4.9 new event packet transmissions......................................................................9 2.5 event timers ................................................................................................................ .10 2.6 synchronous ram and packet control .........................................................................11 2.7 clock synchronization logic ......................................................................................... 11 2.8 smi logic ................................................................................................................... ...11 2.9 miscellaneous logic ...................................................................................................... 12 3.0 signal description .......................................................................................................... ..13 3.1 signal type definition ..................................................................................................13 3.2 clock signals .............................................................................................................. ..13 3.3 smb interface signals .................................................................................................. 13 3.4 82558 b-step flash interface signals .......................................................................... 14 3.5 eeprom interface si gnals ..........................................................................................15 3.6 alert/sos events signals ............................................................................................. 15 3.7 miscellaneous signals .................................................................................................. 15 3.8 power and ground signals ..........................................................................................16 4.0 configuration and status registers .......................................................................17 4.1 register bit types ........................................................................................................1 7 4.2 register 0h; revision id................................................................................................17 4.3 register 1h; event status..............................................................................................17 4.4 register 2h; event polarity ............................................................................................18 4.5 register 3h; event mask ...............................................................................................19 4.6 register 4h; smi mask ..................................................................................................19 4.7 register 5h; watchdog status byte ..............................................................................20 4.8 register 6h; watchdog timer........................................................................................20 4.9 register 7h; heartbeat timer ........................................................................................20 4.10 register 8h; retransmission timer ...............................................................................21 4.11 register 9h; control ......................................................................................................2 2 4.12 register ah; software status byte 1 .............................................................................22
alert on lan* asic networking silicon iv datasheet contents 4.13 register bh; software status byte 2 ............................................................................. 23 4.14 register ch; eeprom access ..................................................................................... 23 4.15 register dh; test mode ................................................................................................ 23 5.0 reset and test modes ...................................................................................................... 25 5.1 reset mode .................................................................................................................. .25 5.2 manufacturing test mode.............................................................................................. 25 5.2.1 nand tree....................................................................................................... 25 5.2.2 tri-state............................................................................................................25 5.3 vector test mode .......................................................................................................... 26 5.3.1 vector input interface .......................................................................................26 5.3.2 vector output interface .................................................................................... 26 6.0 electrical specifications ............................................................................................. 27 6.1 recommended operation conditions .......................................................................... 27 6.2 absolute maximum ratings .......................................................................................... 27 6.3 dc characteristics ....................................................................................................... 27 7.0 packaging information ................................................................................................... 29 8.0 appendix a: alert on lan supporting hardware .................................................31
datasheet 1 networking silicon alert on lan* asic 1.0 introduction the alert on lan asic is intended to provide system manageability function to a desktop platform when used in conjunction with the intel 82558 b-step (82558b) fast ethernet controller. together, these two integrated circuits (ics) provide a management interface between a remote management console or server and the client system. additional hardware is required to provide the alert on lan asic with system monitoring instrumentation (for example, over-voltage or over- temperature indications). the alert on lan asic is not a stand alone device and requires the 82558b, a 64x16 eeprom, environmental ics, and support software to create a functional management solution. a more detailed description of the eeprom and environmental ics and other external components can be found in section 8.0, appendix a: alert on lan supporting hardware on page 31 . 1.1 alert on lan overview the primary function of the alert on lan asic is to provide a transmit stream to the 82558b, which transmits alert (sos) packets or heartbeat (presence) packets. the alert on lan asic is responsible for transmitting these packets when software is unable to (for example, during a low power state or system failure). the alert on lan asic communicates to the system through a system management bus (smb), which is a subset of the phillips i 2 c** interface. the smb typically connects to the pci-to-isa/ ide xcelerator (piix4), which is accessible by the system and through the basic input/output system (bios). communication between the alert on lan asic and the 82558b is through an 8-bit wide parallel data interface plus supporting control signals. the alert on lan asic uses this interface to transfer data for the transmission of packets, alert and heartbeat, to the 82558b. the alert on lan asic transfers packets due to either internal or external events. external events are detected through five dedicated pins of the alert on lan asic; internal events are generated by either a set of timers or support software. the alert on lan asic contains configuration registers to enable or disable events and store packet information. since packets must be internet protocol (ip) routeable, the packet headers are stored in the alert on lan asic. the alert on lan asic does not have the resources necessary to create the correct ip packets and relies on supporting software and the ip stack to supply it with the appropriate information. an external eeprom is used to provide default configuration information to the alert on lan asic. it also provides the only method for loading a packet structure and header into the alert on lan asic. this allows the alert on lan asic to power-up into a configured state without the need for software configuration. 1.2 management overview the alert on lan asic/82558b management solution is intended to provide system management capabilities including (but not limited to):
alert on lan* asic networking silicon 2 datasheet ? sos (alert) events transmit sos packets from preboot, the g0 state (working), the g1 state (sleeping), and the g2 state (soft-off) transmit sender identification in sos messages - sos hardware events - chassis intrusion - voltage out of specification - temperature out of specification - lan leash tamper - processor missing - sos software events - os lockup/system hang - failure to boot - bios/system management interrupt (smi) generated exception message - desktop management interface (dmi)/management agent generated exception message ? presence heartbeat with status information 1.3 alert on lan feature set the alert on lan asic includes the following features: ? full system management solution with environmental instrumentation ? 82558 b-step controller compliance only ? smb interface to host ? multiple transmissions of all sos packets ? five external maskable sos events ? automatic heartbeat generation when system is in sleep or shutdown modes ? watchdog timer for detecting system hang ? power plane signal detection for low power state status ? clock synchronization and smooth transition logic 1.4 specifications and standards compliance ? advanced configuration and power interface specification (acpi), revision 1.0 ? intel system management bus (smb) specification, revision 1.0
datasheet 3 networking silicon alert on lan* asic 2.0 alert on lan asic architectural overview the internal architecture of the alert on lan asic is shown in figure 1, alert on lan asic block diagram on the front cover. 2.1 tco interface the tco interface is a proprietary general purpose input/output (gpio) type of interface to the 82558b. it is an 8-bit parallel data interface along with several control signals. this interface is a unidirectional data bus. data can only be transmitted from the alert on lan asic to the 82558b. the tco read request (trdreq) and tco active (tactive) signals provide a handshaking mechanism that allows a gpio type of interface. the tco marker (tmarker) pin is a signal that indicates whether the data on the bus is a command byte or a data byte. it is used to delineate datagrams on the tco data bus. the only command that the alert on lan asic uses on the tco bus is the transmit command. the format for the transmit command on the tco marker (tmarker) and tco data (tdata[7:0]) lines to the 82558b is shown below. additional signals are used to put the 82558b in or out of tco mode. the tco force (tforce) signal is an active high input that forces the 82558b into tco mode. tforce is also used to end a tco transaction. tforce will be forced inactive when any of the following conditions occur: ? both the pci reset signal (pci_rst#) and main power good signal (pwr_good) are active. ? the 82558 software reset (ctl_558rst) bit in the control register is set ( section 4.11, register 9h; control on page 22 ). ? the transmit enable (ctl_txen) bit in the control register is cleared ( section 4.11, register 9h; control on page 22 ). ? the tco ready active (ctl_trdy) bit in the control register is set ( section 4.11, register 9h; control on page 22 ) and the tco ready (tready#) signal is inactive. tmarker tdata[7:0] bus 104h 0 ffh 000h 0 data byte 0 0 data byte 1 0 data byte 2 0... 0 data byte n 100h
alert on lan* asic networking silicon 4 datasheet ? the alert on lan software reset (tst_rst) bit in the test mode register is set ( section 4.15, register dh; test mode on page 23 ). if a tco transaction is aborted by any of the above mechanisms, except the tst_rst bit, the alert on lan asic will retry the transaction or start a new transaction with the prior status information when the condition that caused the abort no longer exists. the tco status (tstatus#) signal is a pulse that indicates that the 82558b has completely processed the command. in the case of a transmit command, this signal indicates that the packet has been sent on the wire or has been aborted due to transmission errors. this signal indicates to the alert on lan asic that the tforce signal should be de-asserted until the end of the tco cycle. the basic flow for a tco cycle is: 1. the alert on lan asic samples the tactive pin, which should be low prior to any tco cycle. if it is sampled low, the asic asserts tforce to the 82558b. 2. the alert on lan asic asserts trdreq and transfers one byte (a command byte) and tmarker to the 82558b at least two clock cycles after tforce was asserted. 3. the 82558b asserts tactive upon completion of sampling the data. 4. the alert on lan asic samples tactive high and de-asserts trdreq. 5. after the data is read by the 82558b and trdreq is de-asserted, the 82558b de-asserts tact i v e. 6. the alert on lan asic repeats steps two through five for all bytes in a frame with tmarker inactive for data bytes. 7. after the alert on lan asic has completed transferring a whole frame, it de-asserts the tforce pin. the following diagram illustrates tco timing for the alert on lan asic. figure 1. tco timing diagram
datasheet 5 networking silicon alert on lan* asic 2.2 smb interface the smb interface is a slave-only interface. since the alert on lan asic is completely under software control and provides interrupts via the smi output signal (smi#), an smb alert signal is not supported. the smb address the asic responds to is determined at reset time. after an eeprom load has completed (due to hardware or software reset or the main power good signal transition to low), tdata[2:0] are internally latched and are inputs during an eeprom load and reset. the tdata[2:0] lines are multiplexed with the smb address lines 2 through 0 (smb_a[2:0]). the value of these input pins, smb_a[2:0], are used to create the smb address of 0101xxxb, where xxx represents smb_a2, smb_a1, and smb_a0, respectively. these inputs can be configured using pull-up or pull-down resistors. there are default pull-up and pull-down resistors in the silicon to select 110b on smb_a[2:0]. however, the internal pull-up resistors in the device for the smb address are too weak; therefore, all ones for smb address lines require a strong, external pull-up resistor (for example, a value of 2 k w ). resistor values and tolerances are described in section 6.0, electrical specifications on page 27 . more details on smb can be found in the intel system management bus specification, revision 1.0 . for register accesses to the alert on lan asic, a simple set of smb commands are supported: write byte command and read byte command. the command field can be used to access the individual registers. explicit details on the smb cycles and bit definitions are described in section 4.0, configuration and status registers on page 17 . the smb interface can be configured to drive the smb data input/output and smb serial clock pins low when the main power good signal equals 0b by using the drive smb bit of the control register. this is one method of preventing the open drain bus from floating when other smb connections have been powered-off. after reset, the smb interface will be driven low if the main power good signal equals 0b until the control register is read. at this point, the function will depend on the configuration bit. it requires approximately 125 microseconds from reset to read the drive smb bit in the control register. 2.3 eeprom interface note: the alert on lan asic requires a 64x16 eeprom which is separate from the 82558b's eeprom. the eeprom interface is provided to allow default configuration information. this gives the alert on lan asic a default power-up state of enabled and disabled events, ip packet information, individual address, and other configuration data. the alert on lan asic reads information from the eeprom during the following: ? hardware reset . this happens when the alert on lan asic is first powered-up or when the auxiliary power good (aux_good) signal transitions low. the alert on lan asic begins loading the eeprom configuration information as soon as reset is de-asserted. ? software reset . this is accomplished by writing to bit 7 of the test mode register via the smb. after reset has completed, the alert on lan asic begins reading the eeprom. ? hard transition to g2 power state . a hard transition to the g2 power state occurs when the system is powered down before software notifies the alert on lan asic of the transition by
alert on lan* asic networking silicon 6 datasheet setting the acpi state indicator in the control register equal to 10b, where the value of 10b indicates that the system is in the g2 power state. this typically occurs when the system is powered down using the 4-second power switch. loading the eeprom at this time guarantees that the alert on lan asic is placed in a known state since the sudden power loss occurred without software knowledge. the alert on lan asic reads the first 62 words (124 bytes) of the data in the eeprom and leaves the last two words (4 bytes) free for vendor information. to ensure that the eeprom contains valid data, the alert on lan asic uses word 3dh as a checksum. the checksum is a 16-bit value that causes the sum of all of the asics data and checksum (in other words, words 00h through 3dh) to be equal to babah. if the checksum is invalid, the asic resets most of its registers to the reset value to prevent it from entering an unpredictable state due to invalid eeprom data. the reset values for the registers are such that all packet transmissions and smi events are disabled until the eeprom is loaded. smb writes should also be prevented by software during an eeprom load. smb reads are always permitted and should be used to check the eeprom read complete indication bit in the eeprom access register ( section 4.14, register ch; eeprom access on page 23 ) to determine when the eeprom load has completed. the eeprom interface is a microwire** interface that uses 4 control signals: eeprom chip select (eecs), eeprom serial clock (eesk), eeprom data input (eedi) and eeprom data output (eedo). more details on the microwire interface can be found in a microwire eeprom datasheet. a gpio interface is provided to access the eeprom from software. this allows each eeprom bit to be controlled through the smb register interface. this is the only method in which the eeprom can be programmed. 2.4 event interface 2.4.1 new event definition and results there are two components of the event interface. the first portion is the occurrence of an event. an event occurrence happens any time an event is caused: an event pin is at the active level, a software event is set via an smb write, or the watchdog timer expires. if the eeprom does not load, each of these events will be set in the event status register when they happen. the second part of the event interface is a new event . the term new event refers to any event occurrence that initiates a new packet to be generated and transmitted, regardless of whether a packet is currently being transmitted or not. a new event occurs whenever one of the following happens: ? a bit in the event status register changes from inactive to active and the event mask register bit is already enabled for this event. this occurs any time an unmasked event becomes active and the status bit was previously 0b, either because the event did not happened before or because software cleared it. ? the event status register is already set for a particular event, and the event mask is changed from inactive to active. since an event that occurs is stored in the event status register, the event does not have to be currently active in order to produce a new event. ? for a software event, a new event occurs whenever software writes a 1b to the software event status bit in the event status register.
datasheet 7 networking silicon alert on lan* asic all of the above are considered new events because they initiate a new packet transmission and interrupt any current transmissions. section 2.4.9, new event packet transmissions on page 9 describes new event occurrences in more detail. note: a heartbeat does not cause a new event. although it can initiate a packet, it does not interrupt current packet transmissions. if it does initiate a packet, the quantum field will be incremented for that new packet. if the heartbeat occurs within the new event packet transmission window (three packets including the time period between the three packets), the current heartbeat will be ignored. the other reason that a heartbeat is not a new event is because it only causes a single packet to be transmitted, rather than three. 2.4.2 external events the external events are level inputs that cause alert packets to be sent by the alert on lan asic. the active level (polarity) of the signals is configurable through the polarity register, which is written to by the eeprom and smb writes. each hardware event is latched in the event status register after it has occurred, regardless of the event mask or smi mask registers. to clear the event and smi, if enabled, a 1b must be written to the appropriate status register bit. the event mask register selects the events that can cause an alert packet transmission as well as masking the status bits into the packet payload. the smi mask register selects the events that can cause an smi event. both of these registers are loaded by the eeprom and are configurable through the smb interface. every time a new event is activated, the alert on lan asic sends an alert as soon as possible (the 82558b can invoke wait states). at the same time, the retransmission timer starts. at the expiration of this timer, a second identical packet is sent followed by a third packet after the same timer interval. whenever a new event is activated, this sequence begins again. the asic does not continually send alert packets while the level input is active. this helps reduce the amount of redundant management and network-generated traffic. alert packets always take priority over heartbeat packets. if an event occurs, three alert packets are sent along with the retransmission delays before another heartbeat packet is sent. the retransmission timer starts when the packet is queued to be transmitted. if the packet has not been transmitted by the time the retransmission timer has expired, the next packet will not be transmitted. this is highly unlikely to occur; however, it is possible if the 82558b delays the transmission of the packet. possible delays may include an eeprom read or collision back-off. there are five separate external level events: 1. cover tamper . this indicates that the cover has been opened or tampered with. 2. environmental smi . this indicates that the environmental control ic has generated an smi event. 3. bti temperature . this indicates that the environmental control ic has generated an smi event. 4. lan leash . this indicates that the lan has lost its link. this event signal uses a different interface than other events. if enabled, the detection of a link that has been down for five to ten seconds generates an event; however, the alert on lan asic does not transmit unless the link is currently valid. 5. processor missing . this indicates that the processor is not installed. although these events are defined, they can be used for any event as long as the corresponding software can function properly.
alert on lan* asic networking silicon 8 datasheet 2.4.3 event 1, sticky latch clearing mechanism the event_1 input signal to the alert on lan asic is designed to work with an event that is stored in a sticky latch. this event can be configured to clear the sticky latch by driving the opposite polarity on the event_1 pin. if configured, this will occur when the event status register for event_1 is cleared by writing a 1b to this bit. the alert on lan asic will drive the event_1 signal for a minimum of 20 ms, allowing plenty of time for the sticky latch to clear. section 8.0, appendix a: alert on lan supporting hardware on page 31 describes the sticky latch in more detail. with the exception of the sticky latch clearing mechanism, the event 1 input behaves similar to the other events. to enable the clearing mechanism of the event 1 input, the pol_clrev1 bit of the polarity register must be set. if it is desired not to use a sticky latch on event 1, the clearing mechanism can be disabled by clearing the pol_clev1 bit. 2.4.4 event 4, link detect and packet transmission interrupt the event 4 input is designed for use with the link status output from the 82558b. there are two special enable functions available with this event. first is the method of detecting a lost link. if configured, the alert on lan asic will only cause an event 4 in the event status register if it detects an inactive link (based on polarity setting) for two consecutive timer ticks separated by 5.4 seconds. the window of time that the event will detect link loss is between 5.4 through 10.8 seconds since the tick time and link loss events are not synchronous to each other. this feature is required to prevent events on phy resets and 82558b resets, which should produce an invalid link for approximately 3 seconds. the second feature of the event_4 input signal is its ability to cancel or disable packet transmissions across the tco interface whenever the event_4 pin is active. an active event on event_4 indicates that link is down, which will obviously prevent packet transmission on the network, even though the tco transaction may be successful. any packet currently being transmitted will be interrupted and retransmission will occur when link returns. the above two features cause the event_4 input to cause the alert on lan asic to behave differently than it would for other events. in order to activate these features, the pol_lnkev4 bit in the polarity register must be set. if it is desired not to use these features, this bit must be disabled. since link is always lost when power is completely off (g3 state), this event is preset in the event status register, causing a new event (if the event mask is set appropriately) when the alert on lan asic is powered up. note: a software reset will not preset or clear this bit. if this feature is not desired, then the event_4 status bit can be cleared before the mask is enabled. 2.4.5 watchdog event the watchdog event is similar to other events, except that it is caused by an internal timer expiring. the watchdog event can be used to notify the network console when the monitored machine hangs during boot-up. for example, the timer can be set and enabled upon initial power-up. if the system reaches a specified point during boot-up, bios can disable the watchdog timer, preventing a watchdog event. if the system hangs before this point in boot-up is reached, the watchdog timer will time-out and notify the network console.
datasheet 9 networking silicon alert on lan* asic since a hard g2 transition can happen without software knowledge, it is important to disable watchdog events during g2. this is done by temporarily disabling the watchdog enable while the pwr_good signal equals 0b. this disables the watchdog timer during g2, and if a hard g2 transition occurs, an eeprom load will reload the watchdog timer and possibly set it to be enabled. at the point that the pwr_good signal transitions high, the watchdog timer becomes enabled (if configured to be enabled) and starts counting from its initial loaded value, essentially restarting the boot-up time-out timer. 2.4.6 software event the software event also has unique functionality due to its special purpose. the event status bit is set when a 1b is written to the software status event bit of the event status register. after three packets have been transmitted successfully, this bit is cleared in the event status register. however, a write of 1b at any time to this bit will cause a new event and cause the asic to start transmitting a new series of event packets with the current software information. software can detect which packet is in progress by monitoring the ctl_rtcnt bits of the control register. 2.4.7 polarity functionality for the six external events, the event polarity register informs the alert on lan asic whether a particular event is active high or low. the top two bits of the event polarity register enable the special features available for events 1 and 4 (described above). 2.4.8 event status mask and smi mask the event mask register selects the events that can cause an sos packet transmission as well as masking the status bits into the packet payload. the smi mask selects the events that will cause an smi. both of these registers are loaded by the eeprom and configurable through the smb interface. while the eeprom is being read, no events will be observed by the alert on lan asic, regardless of either of the mask settings. after the eeprom is finished loading, the alert on lan asic allows the events to enter into the status register, subsequently causing a packet to be sent or the smi output to be asserted depending on the setting of the mask registers. 2.4.9 new event packet transmissions every time a new event occurs, the following sequence of events will be performed: 1. any current packet transmission will be aborted. 2. the quantum counter will increment. 3. the ctl_rtcnt counter value will be reset to 11b. 4. the retransmission timer will be reloaded. 5. data is latched internal to alert on lan asic for packet creation: high byte of quantum counter low byte of quantum counter masked event status register control register (since it is latched, all 3 packets will show rtcnt equals 11b)
alert on lan* asic networking silicon 10 datasheet high byte of software register low byte of software register watchdog data 6. the udp checksum word will be incrementally calculated based on the data above and written at the appropriate udp checksum location. 7. assuming that a packet can be sent (ctl_txen is set, the eeprom has completed loading, 82558_rst is not active, tready# is not active or the ctl_trdy is clear, and link is valid or pol_lnkev4 is clear), the complete packet, internally latched, will be transmitted to the 82558 via the tco bus. 8. once the packet has been successfully transmitted to the 82558b, the ctl_rtcnt counter will be decremented one. the sequence is 11b, 10b, 01b, 00b. 9. when the retransmission timer is expired, execution will begin at step 7 if the ctl_rtcnt counter value does not equal 00b. if ctl_rtcnt equals 00b after the previous packet has been transmitted (3 identical packets have been transmitted), then packet transmissions stop until the next new event or a heartbeat occurs. since this process is always restarted when a new event occurs, it is possible to skip quantum numbers on the network transmissions. for example: ? event a occurs and causes 3 packets with quantum n to transmit. ? event b occurs and starts transmitting 1 packet with quantum n+1 . ? event c occurs in the middle of the packet from event b. this causes this packet transmission to halt, and a new packet is started with quantum n+2 . therefore, the packet with quantum n+1 is never actually fully transmitted. note: sos alerts will always take priority over heartbeat packets. if an event occurs, three sos packets will be sent along with the re-transmission delays before another heartbeat packet is transmitted. 2.5 event timers the event timers consist of a clock divider circuit and three timers within the alert on lan asic: 1. heartbeat timer . this timer controls the heartbeat status packet frequency. the alert on lan asic transmits one packet per heartbeat timer expiration. 2. watchdog timer . this is a configurable timer used to time-out on critical events (for example, failed os boot, post failure, os hang, etc.). 3. retransmission timer . this timer controls the frequency of the retransmission of sos packets. the alert on lan asic transmits an alert packet three times. the watchdog timer event is automatically masked by hardware while the main power good signal equals 0b. this prevents the watchdog timer from failing when system power is lost. the watchdog timer is used only to detect an os hang.
datasheet 11 networking silicon alert on lan* asic 2.6 synchronous ram and packet control there is a 128-byte synchronous ram block inside of the alert on lan asic primarily used for storing the packet to be sent. the contents of the eeprom are directly loaded into ram when an eeprom load occurs. the packet control block is responsible for adding tco data and dynamic packet data to the ram and controlling the tco block to send each packet out to the tco interface. 2.7 clock synchronization logic the clock synchronization logic is used to provide a smooth transition of clocks for the 82558b. since the 82558b requires a clock for tco support in low power states, clock synchronization logic is a necessity. this logic ensures that the transition between the pci clock and the 25 mhz clock generated by the 82558b is smooth and non-glitching. this assures that the 82558b continues to operate in a known state. pci_ck and b25_ck are the pci and the 82558b 25 mhz output clocks, respectively. the alert on lan asic must monitor both in order to provide a smooth transition between both clocks. both clocks are required during the power state transition (in other words, pwr_good transitions low). after the main power good signal transitions low at least 3 pci clocks are required to switch from the pci clock to the 82558bs 25 mhz clock. pci_sel and b25_sel are the pci and the 82558b 25 mhz clock gates, respectively. these outputs control analog switches that can turn the clocks on or off. note: the analog switches used must be selected carefully to guarantee that the pci clock skew specifications are not violated. 2.8 smi logic the smi# signal is asserted (active low) if the event status and the smi mask bits are set for any particular event, with the exception of a software event. the software event cannot be used to generate an smi. since the smi# requires both the event status and the smi mask for one event to be set, clearing any one of these two bits will de-assert the smi# signal if it is the only event causing the smi#. if one external event has occurred and the smi mask bit is set, the smi# signal will be active. if the event is cleared by writing a 1b to the appropriate status bit, the event will be cleared in the alert on lan asic. however, if the event is still active, it will be set again in the event status register. the net result is that the smi# line will pulse inactive for a single 25 mhz clock cycle. if this is undesired, software will need to take steps to avoid this. this can be achieved by disabling the smi mask bit or ensuring that the external event is no longer active. smi events can happen independently or jointly with packet transmission events since each has its own smi mask register.
alert on lan* asic networking silicon 12 datasheet 2.9 miscellaneous logic the alert on lan asic has a block of miscellaneous logic, consisting of registers, reset circuitry, and pwr_good monitoring. the power monitoring is significant and explained in this section. the alert on lan asic monitors two input signals, pwr_good and aux_good, to indicate the status of the main power supply and the auxiliary power supply, respectively. these signals allow the alert on lan asic to determine the state of the power supplies and control the 82558b appropriately. this enables the alert on lan asic to determine whether or not the pci interface is active. in order to guarantee that altrst# is asserted before isolate#, the alert on lan asic provides the combinational logic driven by pwr_good and aux_good to control the isolate# output. this is important since the 82558b will not be able to propagate a reset unless four clock cycles are present while altrst# or pci_rst# is active and isolate# is inactive. another main function of the alert on lan asic is to determine when power has been lost or attained to the main power plane. this allows the alert on lan asic to enable or disable certain events as necessary for the different power states. the alert on lan asic monitors the main power good signal at all times and is designed to detect when the system has been powered down with or without software knowledge. when the system is powered down normally, software will set the acpi state in the acpi state indicator bits of the control register to acpi g2 state (10b), anticipating a power-down. from this state, the alert on lan asic will continue operating normally if the system is powered down (for example, the main power good signal transitions from high to low). however, if the acpi system state is not set to g2 when the main power good signal transitions from high to low, the alert on lan asic will force a re-read of the eeprom to load its default values. this ensures that the alert on lan asic will be able to operate in a known state, rather than an unpredictable state due to the software unaware power-down. pci_rst# is used as an input to the alert on lan asic and as a stimulus to reset the 82558b with the 82558_rst# signal. in a system with the alert on lan management solution, it is undesirable to reset the 82558b while the main power good signal is low. the alert on lan asic only allows pci_rst# to assert 82558_rst# when the main power good signal is 1b. this input can also cause the alert on lan asic to terminate any tco transactions with the 82558b until it can continue at a later time. the alert on lan asic offers software the capability of resetting the 82558b through the use of the ctl_558rst bit in the control register ( section 4.11, register 9h; control on page 22 ). the main power good signal effect on the propagation of pci_rst# to 82558_rst# is important since piix4 will assert a pci_rst# when power is being lost. however, pci_rst# will reset the 82558b which is undesirable. therefore, the alert on lan asic uses the main power good signal to determine if pci_rst# should be propagated or not. this assumes that the main power good signal is de-asserted before pci_rst#.
datasheet 13 networking silicon alert on lan* asic 3.0 signal description 3.1 signal type definition 3.2 clock signals 3.3 smb interface signals symbol name description i input input is a standard input. o tot em pol e output totem pole output is a standard active driver. i/o input/output this signal is used for input and output to the device. od open drain open drain allows multiple devices to share as a wired or gate. cmos cmos input buffer voltage detail for the cmos input buffer are described in section 6.3, dc characteristics on page 27 . ttl ttl input buffer voltage detail for the cmos input buffer are described in section 6.3, dc characteristics on page 27 . s schmitt-trigger input this is used as schmitt-trigger input. pu pull-up resistor pull-up resistance in the silicon is present. pd pull-down resistor pull-down resistance in the silicon is present. n ma output buffer drive in milliamps, where n is an integer value. symbol pin type name and function pci_ck 40 i, pd, cmos pci clock. this signal is the pci clock from the pci interface. the frequency range is 0 to 33 mhz. b25_ck 42 i, cmos 82558 generated clock. this is a 25 mhz clock input provided by the 82558b. this clock is expected to operate at all times at a constant 25 mhz frequency, unless power to the alert on lan asic is lost. pci_sel 41 o, 6 ma pci_ck select. this pin is asserted high (active) when pci_ck is enabled to the 82558b. b25_sel 43 o, 4 ma b25_ck select. this pin is asserted high (active) when b25_ck is enabled to the 82558b. symbol pin type name and function smb_scl 36 i/o, od, ttl, s, 4 ma smb serial clock. this pin is the clock signal provided by the system in order to communicate over smb. this pin is used as output when driven low during reset and while pwr_good is equal to 0b if enabled (drive smb bit in the control register). otherwise, the smb_scl signal is used as input.
alert on lan* asic networking silicon 14 datasheet 3.4 82558 b-step flash interface signals smb_sda 37 i/o, od, ttl, s, 4 ma smb data input/output. this pin is the data signal used to transfer data over the smb. it is used as output when driven low during reset and while pwr_good is equal to 0b if enabled (drive smb bit in the control register). otherwise, the smb_sda signal is used as input and output for smb data. symbol pin type name and function tdata7 (test_en) 13 i/o, pu, cmos, 2 ma tco data bus [7]. during reset (aux_good = 0b), this pin acts as the test enable (test_en) input. on the rising edge of reset, the test enable is latched and active. a high value causes the test mode to be enabled. otherwise, tdata7 is used for the tco data bus. tdata6 (test_mode) 12 i/o, pu, cmos, 2 ma tco data bus [6]. during reset (aux_good = 0b), this pin acts as the test_mode input. on the rising edge of reset, the test mode is latched and active. otherwise, tdata6 is used for the tco data bus. tdata5 tdata4 tdata3 9 8 7 o, 2 ma tco data bus [5:3]. the data bus is used to transmit packets from the alert on lan asic to the 82558b. this data is only valid when the tforce signal is asserted. tdata2 tdata1 tdata0 (smb_a[2:0]) 4 3 2 i/o, pu/ pd, cmos, 2 ma tco data bus [2:0]. during reset and eeprom load, these pins act as inputs. at the end of an eeprom load, the smb address is latched and tdata[2:0] acts as output for smb_a[2:0]. the default address is 110b via internal pull-up and pull-down resistors. otherwise, tdata[2:0] is used for the tco data bus. tmarker 11 o, 2 ma tco marker. the marker strobe is used to indicate the start and end of a tco command on the tdata[7:0] bus. when tmarker is active, this indicates that tdata contains a tco command byte (not a data byte). trdreq 14 o, 2 ma tco read request. when trdreq is asserted (active high), it indicates that the alert on lan asic has one byte to be transferred to the 82558b. trdreq is de-asserted upon acknowledgment from the tactive signal. tactive 1 i, cmos tco active. tactive is asserted by the 82558b to indicate that the 82558b has acknowledged a trdreq transaction (tforce = 1b) or that the 82558b is not ready for a tco cycle (tforce = 0b). tforce 44 o, 2 ma tco force. tforce is a control signal used to force the 82558b into tco mode. when the 82558b is forced into tco mode, the tdata[7:0] and tmarker interface on the 82558b is activated. tstatus# 10 i, cmos tco status. tstatus# is an active low input indicating that the 82558b has completed its current tco command. this indication is necessary to mark the end of packet transmission. tready# 35 i, cmos tco ready. the tco ready signal is an active low input indicating the power state of the 82558b. if it is asserted, the 82558b is in a low power state (d1, d2, or d3). this input indicates when the alert on lan asic should de-assert the tforce signal in wake-up scenarios symbol pin type name and function
datasheet 15 networking silicon alert on lan* asic 3.5 eeprom interface signals 3.6 alert/sos events signals 3.7 miscellaneous signals symbol pin type name and function ee_cs 18 o, 1 ma eeprom chip select. eeprom chip select is used to control access to the eeprom. ee_sk 19 o, 1 ma eeprom shift clock. the ee_sk signal is used to shift data in and out of the eeprom. ee_do 21 i, ttl, pu eeprom data out. serial data output from the eeprom. ee_di 20 o, 1 ma eeprom data in. serial data input to the eeprom. symbol pin type name and function event_1 22 i/o, ttl, s, 4 ma event_1 - cover tamper. level input that causes alert 1 packet transmission. this pin can be used as output as a clearing mechanism on external sticky logic. event_2 23 i, ttl, s event_2 - env_smi. level input that causes alert 2 packet transmission. event_3 24 i, ttl, s event_3 - bti_temperature. level input that causes alert 3 packet transmission. event_4 25 i, ttl, s event_4 - lanleash. level input that causes alert 4 packet transmission. event_5 26 i, ttl, s event_5 - processor missing. level input that causes alert 5 packet transmission. reserved 29 n/a this pin is reserved and should be pulled down to 0b via a 220 w resistor. symbol pin type name and function pci_rst# 32 i, ttl pci reset. the pci_rst# pin is an active low input signal from the pci interface. it propagates to the 82558b through the 82558_rst# line if pwr_good is active. it is also used as an indication to the alert on lan asic that the 82558b is being reset. 82558_rst# 15 o, 2 ma 82558 reset. the 82558 reset signal is an active low reset. it is driven when the pci_rst# signal is active and the pwr_good signal is active. it is also driven when an 82558b software reset is triggered through the internal registers. isolate# 33 o, 2 ma isolate output. this output signal is used to isolate the pci bus on the 82558b. it implements the 82558b wake on lan* (wol) circuitry to guarantee that the altrst# signal of the 82558b is asserted before isolate# is asserted. this is based on the pwr_good and aux_good signals. smi# 34 o, od, 2 ma smi output. the smi# signal is asserted by the alert on lan asic for various events depending on the smi mask register settings. smi# is de-asserted by clearing the events or masks in the alert on lan asic's status registers.
alert on lan* asic networking silicon 16 datasheet 3.8 power and ground signals symbol pin type name and function pwr_good 31 i, ttl, s main power good. this signal indicates that the main +5 v power supply is available. aux_good 30 i, ttl auxiliary power good. this signal indicates that an auxiliary power supply is available. it is also used as an active low reset to the alert on lan asic. vdd 5, 16, 27, 38 power. +5 v 5% gnd 6, 17, 28, 39 ground. 0 v
datasheet 17 networking silicon alert on lan* asic 4.0 configuration and status registers the alert on lan asic configuration and status registers are accessible through the smb. the smb cycles for register reads and writes are shown below. 4.1 register bit types 4.2 register 0h; revision id the revision id register identifies the alert on lan asic and its silicon revision. it is intended to provide software a method of accessing this information. 4.3 register 1h; event status the event status register holds the status of all events. the watchdog event and events one through five are set when the event occurs and remain set until software clears them by writing a 1b to the event status bit. the software event, bit 7, is set via software causing an event and self-clears after three packet transmissions. however, writing a 1b to the software event bit always causes a new packet to be started, regardless of how many packets have been transmitted. if software wants to send only one packet before it causes a new software event, it may monitor the packet retry counter in the retransmission count field (ctl_rtcnt) in the control register. when sta_ev1 figure 2. smb register read and write cycle s ap address xxxxrr a ap address a rxb y te /a p 0 s ap address xxxxrrrr a tx b y te p 0 a s 1 read b y te: write b y te: a a symbol description r/w read/write ro read only sc self clearing r/w1 read/write 1b to clear ee( x ) default value from eeprom with a value of x if the eeprom is invalid hwrst hardware reset only (software reset has no effect) bits name type name and description default 7:3 ap_id ro alert on lan id. this register contains the 11010b binary code identifying the alert on lan asic. 11010b 2:0 ap_rev ro alert on lan silicon revision. this register contains the three bit coded silicon revision. xxxb
alert on lan* asic networking silicon 18 datasheet is cleared by writing a 1b to bit 0 and the clear sticky latch polarity bit (pol_clrev1) in the event polarity register equals 1b, the event_1 pin outputs the opposite of the event polarity register bit between 20 and 40 milliseconds. 4.4 register 2h; event polarity the event polarity register is used to set the polarity of the event inputs. this flexibility allows the alert on lan to handle external interfaces that are either active low or active high. bits name type name and description default 7sta_swe r/w sc software event status. this bit is set if software causes an event. it can also be forced by writing a 1b to this bit. 1 = force software event this bit self-clears after three software event packet transmissions. 0b 6 sta_wdg r/w1 watchdog event status. this bit is set if the watchdog timer has expired. writing a 1b to this bit clears it. 1 = watchdog timer expired 0b 5 reserved this bit is reserved and should be set to 0b. 0b 4 sta_ev5 r/w1 event_5 status. this bit indicates status of event 5, processor missing. it is set if the processor is not installed. writing a 1b to this bit clears it. 1 = event_5 occurred 0b 3 sta_ev4 r/w1 event_4 status. this bit indicates status of event 4, lan leash. it is set if the lan has lost its link. writing a 1b to this bit clears it. 1 = event_4 occurred 1b a 2 sta_ev3 r/w1 event_3 status. this bit indicates status of event 3, bti temperature. it is set if the bti temperature is out of the specified range. writing a 1b to this bit clears it. 1 = event_3 occurred 0b 1 sta_ev2 r/w1 event_2 status. this bit indicates status of event 2, env_smi. it is set if the hardware monitoring device has an smi event. writing a 1b to this bit clears it. 1 = event_2 occurred 0b 0 sta_ev1 r/w1 event_1 status. this bit indicates status of event 1, cover tamper. it is set if the cover has been opened or tampered with. writing a 1 to this bit clears it. 1 = event_1 occurred 0b a. a hardware reset causes this bit to return to its default value of 1b; a software reset leaves this bit value unaffected. bits name type name and description default 7pol_clrev1r/w clear sticky latch. this bit enables the event_1 pin to drive out and clear a sticky latch. this bit is enabled when set to 1b. ee(0) 6pol_lnkev4r/w link status. this bit enables the event_4 pin to act as link status input. when it is enabled, the event_4 status is only latched if the event is active for five to ten seconds, and packet transmission is valid only when link is good. ee(0)
datasheet 19 networking silicon alert on lan* asic 4.5 register 3h; event mask the event mask register is used to mask events from transmitting sos packets. if the event bit is set to 1b, the event will cause an sos packet. if it is 0b, it will not. this mask also prevents the event from showing up in the status byte in the packet when the bit is 0b. note: the watchdog event is masked by hardware when the pwr_good signal is low. 4.6 register 4h; smi mask the smi mask register is used to mask events from causing an system management interrupt (smi). if the event bit is set to 1b, the event will cause an smi. if it is set to 0b, it will not. 5 reserved ro this bit is reserved and should be set to 0b. 0b 4 pol_ev5 r/w event_5 polarity. 1 = active high 0 = active low ee(0) 3 pol_ev4 r/w event_4 polarity. 1 = active high 0 = active low ee(0) 2 pol_ev3 r/w event_3 polarity. 1 = active high 0 = active low ee(0) 1 pol_ev2 r/w event_2 polarity. 1 = active high 0 = active low ee(0) 0 pol_ev1 r/w event_1 polarity. 1 = active high 0 = active low ee(0) bits name type name and description default bits name type name and description default 7 reserved ro this bit is reserved and should be set to 0b. 0b 6 msk_wdg r/w watchdog event mask. 1 = watchdog timer packet enabled ee(0) 5 reserved r/w this bit is reserved and should be set to 0b. ee(0) 4 msk_ev5 r/w event_5 mask. 1 = event_5 transmit packet enabled ee(0) 3 msk_ev4 r/w event_4 mask. 1 = event_4 transmit packet enabled ee(0) 2 msk_ev3 r/w event_3 mask. 1 = event_3 transmit packet enabled ee(0) 1 msk_ev2 r/w event_2 mask. 1 = event_2 transmit packet enabled ee(0) 0 msk_ev1 r/w event_1 mask. 1 = event_1 transmit packet enabled ee(0) bits name type name and description default 7 reserved ro this bit is reserved and should be set to 0b. 0b 6 smi_wdg r/w watchdog event smi mask. 1 = watchdog timer smi enabled ee(0) 5 reserved r/w this bit is reserved and should be set to 0b. 0b 4 smi_ev5 r/w event_5 smi mask. 1 = event_5 smi enabled ee(0) 3 smi_ev4 r/w event_4 smi mask. 1 = event_4 smi enabled ee(0) 2 smi_ev3 r/w event_3 smi mask. 1 = event_3 smi enabled ee(0) 1 smi_ev2 r/w event_2 smi mask. 1 = event_2 smi enabled ee(0) 0 smi_ev1 r/w event_1 smi mask. 1 = event_1 smi enabled ee(0)
alert on lan* asic networking silicon 20 datasheet 4.7 register 5h; watchdog status byte the watchdog status byte register is used to provide more watchdog information to the packet recipient. it provides a means of identifying the cause of the watchdog event (such as os hang, failed boot, etc.). this byte is transmitted with each packet. note that some software implementations may use this byte as additional information for a software event. this requires that the watchdog event is disabled (masked) during these transmissions since this byte is designated for watchdog data when the watchdog event bit is set in the event status register. 4.8 register 6h; watchdog timer the watchdog timer register is used to enable and configure the time-out value of the watchdog timer. the watchdog time-out value can only be written to when the timer is disabled. however, the value can be written and the timer enabled in a single smb write. the timer begins counting down from the value received during a write to the register. when the timer reaches zero, a new event is caused and the timer begins counting down again. any write to this register while it is enabled will reload the time-out value. a read from the register will result in the current value of the timer. note: it is not recommended to set the time-out value to 00h. although an event will not be caused immediately, one will be caused at the first incident if the timer is loaded with a nonzero value and enabled with one smb write. 4.9 register 7h; heartbeat timer the heartbeat timer register is used to enable and configure the time-out value of the heartbeat timer. the heartbeat time-out value can only be written when the timer is disabled. however, the value can be written and the timer enabled in a single smb write. bits name type name and description default 7:0 wdg_dat r/w watchdog status. this register is byte-wide and indicates the status for transmitted sos packets on watchdog timer expiration. ee(40h) bits name type name and description default 7:1 wdg_val r/w watchdog timer value. this value loads in 43-second resolution with a range from 43 seconds to 92 minutes. it can only be written to while the timer is disabled. this timer has an accuracy of its value minus one tick, where one tick is equal to 43 seconds. ee(0000001b) 0 wdg_ena r/w timer enable. 1 = enable/reset counter 0 = disable counter ee(0)
datasheet 21 networking silicon alert on lan* asic the timer begins counting down from the value received during a write to the register. when the timer reaches zero, a heartbeat event is caused and the timer begins counting down again. any write to this register while it is enabled reloads the time-out value. a read from the register results in the current value of the timer. note: it is not recommended to set the time-out value to 00h. although an event will not be caused immediately, one will be caused at the first incident if the timer is loaded with a nonzero value and enabled with one smb write. 4.10 register 8h; retransmission timer the retransmission timer register is used to configure the time-out value of the retransmission timer. the retransmission timer is always enabled and is reloaded when a new event occurs. unlike the watchdog timer and heartbeat timer, the retransmission timer only reloads the time- out value when it expires or a new event occurs, not every time a write is done. note: a read from the retransmission timer register results in the current time-out value, not the current timer value. bits name type name and description default 7:1 hbt_val r/w heartbeat timer value. this value loads in 43-second resolution with a range from 43 seconds to 92 minutes. it can only be written to while the timer is disabled. this timer has an accuracy of its value minus one tick, where one tick is equal to 43 seconds. ee(0000001b) 0 hbt_ena r/w timer enable. 1 = enable/reset counter 0 = disable counter ee(0) bits name type name and description default 7:1 rtm_val r/w retransmit timer value. this value loads in 2.7- second resolution with a range from 2.7 seconds to 5.7 minutes. it can only be written to while the timer is disabled. this timer has an accuracy of its value minus one tick, where one tick is equal to 2.7 seconds. ee(0000001b) 0 rtm_rsvd ro this bit is reserved and should be set to 0b. 0b
alert on lan* asic networking silicon 22 datasheet 4.11 register 9h; control the control register is used to provide miscellaneous control and status functions. the retransmission packet count, tco interface active indication, and apci states can be obtained from the control register. also, the 82558b can be reset, packet transmission can be enabled or disabled, the behavior of the tready# signal can be set, and the acpi state can be changed through this register. 4.12 register ah; software status byte 1 the software byte 1 register is used to provide detailed software information to the packet recipient. this byte provides a method of sending specific information from the software and is transmitted with each packet. it is intended to be valid when the software event bit is set in the event status register. bits name type name and description default 7:6 ctl_rtcnt ro retransmission count. these bits indicate which of the three alert on lan packet types are currently being processed and sent. 11 = first packet 10 = second packet 01 = third packet 00 = no sos packets 00b 5ctl_trdy r/w tready# active. when this bit is set, tforce is de- asserted when tready# is asserted high. otherwise, tready# does not affect tforce. ee(0) 4 ctl_558rst r/w 82558 software reset. setting this bit to 1b causes the hardware reset line to be asserted to the 82558b. a 0b value de-asserts the reset. ee(0) 3 ctl_drsmb r/w drive smb. setting this bit to 1b causes the alert on lan asic to drive the open drain smb interface while pwr_good is low. if this bit is a 0b, the smb interface operates as normally expected, regardless of pwr_good. ee(1) 2ctl_txen r/w transmit enable. this bit enables real time control of all alert on lan asic transmission. when active (1b), transmission occurs as normal; otherwise, when inactive (0b), transmission halts. ee(0) 1:0 ctl_acpi r/w acpi state indicator. 00 = g0 power state 01 = g1 power state 10 = g2 power state 11 = preboot. if the acpi state is not g2 and pwr_good transitions from high to low, an eeprom load will occur. thus, this register is reloaded. ee(11) bits name type name and description default 7:0 sws1_dat r/w these bits indicate the status of transmitted sos packets from a software event. 00h
datasheet 23 networking silicon alert on lan* asic 4.13 register bh; software status byte 2 the software byte 2 register is used to provide detailed software information to the packet recipient. this byte provides a method of sending specific information from the software and is transmitted with each packet. it is intended to be valid when the software event bit is set in the event status register. 4.14 register ch; eeprom access the eeprom register is used to give eeprom status and allow access to the individual eeprom pins. eeprom read complete status and invalid checksum status are indicated in this register. a gpio bit interface is provided to allow software to access and write directly to the eeprom. 4.15 register dh; test mode the test mode register is used to access internal test modes of the alert on lan asic and to force a software reset of the asic. bits name type name and description default 7:0 sws2_dat r/w these bits indicate the status of transmitted sos packets from a software event. 00h bits name type name and description default 7 ee_comp ro eeprom read complete indication. this bit is set to 1b after the configuration eeprom read is complete. 0b 6 ee_icksm ro eeprom invalid checksum indication. this bit should only be read after the eeprom read has been completed. 1 = invalid checksum detected 1b a 5:4 reserved ro these bits are reserved and should be set to 00b. 00b 3 ee_do ro eedo input state. this bit indicates ee_do status. xb 2 ee_di r/w eedi output state. this bit sets ee_di status. 0b 1 ee_cs r/w eecs output state. this bit sets ee_cs status. 0b 0 ee_sk r/w eesk output state. this bit sets ee_sk status. 0b a. the default value of ee_icksm is 1b after reset. after valid data has been detected, ee_icksm is set to 0b, valid checksum detected. bits name type name and description default 7tst_rst r/w sc alert on lan software reset. this bit is used to reset the alert on lan. it performs the equivalent of a hardware reset and re-reads the eeprom. this bit self-clears and the reset completes after four clock cycles. 0b 6tst_moder/w test mode. the test mode enable bit provides access into the alert on lan asics vector test mode coverage. 0b
alert on lan* asic networking silicon 24 datasheet 5 tst_frc25 r/w force 25 mhz clock. this bit forces the clock switching mechanism to select the 82558b 25 mhz generated clock. 0b 4 tst_tco ro tco mode active indication. this bit is active while the alert on lan is sending a packet to the 82558b. otherwise, this bit is cleared. 0b 3 tst_fast r/w fast mode. the fast mode enable bit provides quick test modes for test vector coverage 0b 2:0 reserved ro these bits are reserved and should be set to 000b. 000b bits name type name and description default
datasheet 25 networking silicon alert on lan* asic 5.0 reset and test modes 5.1 reset mode when the alert on lan asics aux_good signal is asserted (active low), all internal circuits are reset, except for the test mode circuitry. the aux_good signal is expected to remain low for at least 10 b25_clk cycles before it is completely reset and stable. the pci reset signal (pci_rst#) does not reset the alert on lan asic. however, it is passed through to the 82558 reset signal (82558_rst#) when pwr_good is active. when pwr_good is de-asserted, the 82558_rst# is driven high (inactive). 5.2 manufacturing test mode the alert on lan asic is put into test mode when the tdata7 (test_en) signal, pin 13, is sampled high on the rising edge of reset (aux_good = 0b). also, the value of tdata6 (test_mode) is latched internal to alert on lan asic. the value of this latched signal determines the test mode that is activated (while test_en is asserted). the two test modes supported are: ? nandtree tdata6 latched value = 0b ? tri-state tdata6 latched value = 1b the test mode remains enabled until another reset occurs where tdata7 is sampled low on the rising edge of reset. 5.2.1 nand tree this test mode provides a nand tree path around the periphery of alert on lan asic consisting of all of the alert on lan asic pin inputs as stimuli. the first input on the nand tree is pci_rst#, pin 32, and the output of the nand tree is isolate#, pin 33. the nand tree travels clockwise around the chip (decreasing pin order), including every input buffer, with the exception of the aux_good, b25_clk, and tdata6 pins. aux_good cannot be used as part of the nand tree because it is used as reset, and b25_clk has a special input buffer that cannot use the nand tree. during the test mode, tdata6 is used as a required dedicated input to the process monitor. all input buffers are true buffers except for pci_clk, which is in inverting input buffer. this should be taken into consideration when implementing the test vectors. 5.2.2 tri-state this test mode tri-states all outputs on the alert on lan asic as well as disables all internal pull- up and pull-down resistors.
alert on lan* asic networking silicon 26 datasheet 5.3 vector test mode the alert on lan asic can be put into two different test modes for allowing easier access to registers during testing. by setting tst_mode in the test mode register, the alert on lan asic provides a special parallel data interface for easy input and output. the asic can also be put into a fast mode that internally configures the alert on lan asic such that counters and state machines are free running. this is done by setting the tst_fast bit in the test mode register. these vector test modes are used to provide a method of obtaining better and faster test coverage of internal nodes, helping facilitate higher yields and achieve higher probability of error-free devices on the asic manufacturing line. these modes are not recommended in normal operation of alert on lan asic. note: the vector test mode mode will make the alert on lan asic unusable in its intended operation. these are special modes that are only intended for more efficient test vector coverage. 5.3.1 vector input interface the input interface to the vector test mode uses 9 bits: 8 bits for data and 1 bit to select between an address phase and a data phase. there is no chip select, which means that an address phase or a data phase will occur at every rising edge of the alert on lan asic clock. the 8-bit address/data signals used are tready#, event_6, event_5, event_4, event_3, event_2, event_1, and tstatus#. the order listed shows the bit order with tready# as the most significant bit and tstatus# as the least significant bit. the address/data select input is the tactive signal. when it equals 0b, an address phase occurs on the next rising edge; when the signal is a 1b, a data phase occurs. the addressing scheme for the input interface is described in table 1 . note: this is only an input interface. section 5.3.2, vector output interface describes the output interface in more detail. 5.3.2 vector output interface the output interface in vector test mode uses 8 bits. this output bus is simply a result of the current addresses latched from the vector input interface. for example, if the last address phase on the input vector interface was 10001001b, some propagation delay after this value is latched in on the rising clock edge, the output interface would show the results of the ram, address 09h. the 8-bit data output signals used are tdata[7:0]. this order shows the bit order, where tdata7 is the most significant bit and tdata0 is the least significant bit. table 1. vector input interface addressing scheme data select (tactive) ad[7:0] description 0 1rrrrrrr this is the address phase where rrrrrrr addresses ram. this allows addressing to all 128 bytes of ram. 0 0xxrrrrr this is the address phase where rrrrr addresses the alert on lan asic registers. this addresses up to 32 registers. xx are dont care bits. 1 dddddddd this is the data phase where dddddddd is the data that is written to the previously latched address from an address phase.
datasheet 27 networking silicon alert on lan* asic 6.0 electrical specifications 6.1 recommended operation conditions 6.2 absolute maximum ratings 6.3 dc characteristics table 2. recommended operating conditions symbol parameter min max unit v dd dc voltage supply 4.75 5.25 v ta operating ambient temperature 0 70 c tj junction temperature 150 c table 3. absolute maximum ratings symbol parameter min max unit v dd dc voltage supply -0.3 7.0 v v in input voltage -1.0 v dd + 0.3 v i in dc input pin current -10 10 ma t stg storage temperature -40 125 c r pud pull-up/pull-down resistor 35 65 k w table 4. dc characteristics symbol parameter condition min typ max unit v il voltage input low ttl cmos 0.8 0.2 v dd v v v ih voltage input high ttl cmos 2.0 0.7 v dd v v v t switching threshold ttl cmos 1.5 2.5 v v i in input current: cmos, ttl inputs inputs with pull-down resistors ttl inputs with pull-up resistors v in = v dd or v ss v in = v dd v in = v ss -10 35 -35 1 115 -115 10 222 -214 m a m a m a
alert on lan* asic networking silicon 28 datasheet v oh voltage output high i oh = -1 ma i oh = -2 ma i oh = -4 ma 2.4 2.4 2.4 v v v v ol voltage output low i ol = 1 ma i ol = 2 ma i ol = 4 ma 0.2 0.2 0.2 0.4 0.4 0.4 v v v i oz tri-state output leakage current v oh = v dd or v ss -10 1 10 m a i os output short current a v dd = 5.25 v, v o = v dd ; v dd = 5.25 v, v o = v ss 37 -117 90 -75 140 -40 ma ma i dd quiescent supply current v in = v dd or v ss 26 ma c in input capacitance any input and bidirectional buffer 2.5 pf c out output capacitance any output buffer b 2.0 pf a. i os is a 4 ma output. the output short circuit current for other outputs will scale. b. output using single buffer structure (excluding package). table 4. dc characteristics symbol parameter condition min typ max unit
datasheet 29 networking silicon alert on lan* asic 7.0 packaging information pin allocation is based on a 44-pin thin quad flat package (tqfp). package dimensions and its attributes are shown in figure 3 and table 5 below. notes: 1. coplanarity is the difference between the highest lead and the seating plane, -c-. 2. datums a-b and -d- to be determined at datum plane -h-. 3. datum plane -d- to be determined at seating plane -c-. 4. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 millimeter/0.010 inch per side. dimensions d1 and e1 do not include mold mismatch and are determined at datum plane -h-. 5. details of pin 1 identifier are optional but must be located within the zone indicated. figure 3. dimension diagram for the alert on lan asic
alert on lan* asic networking silicon 30 datasheet 6. datum plane -h- is located at the mold parting line and is coincident with the bottom of the leads where the lead exits the plastic body. 7. the drawing/dimensions are only for reference. for board layout, request a detailed engineering drawing from an lsi logic sales office. note: all measurements are in millimeters. table 5. dimensions for the 44-pin tqfp alert on lan asic symbol min max bsc a--1.60-- a1 0.05 -- -- a2 1.35 1.45 -- b 0.30 0.45 -- d 11.90 12.10 - d1 9.90 10.10 -- e----0.80 e 11.90 12.10 -- e1 9.90 10.10 -- l 0.45 0.75 -- aaa -- 0.10 -- ccc -- 0.10 --
datasheet 31 networking silicon alert on lan* asic 8.0 appendix a: alert on lan supporting hardware the alert on lan asic is not a stand alone device. it requires additional components to create a functional management solution. one possible set of supporting hardware is identified in this appendix. note: supporting hardware sets will differ from implementation to implementation. ? 82558 b-step device the 82558 ethernet lan controller is required for a complete solution. the alert on lan asic is designed to communicate with the proprietary tco interface of the 82558b. the 82558b provides the functionality to transmit data on the network and calculates and adds a 32-bit crc to the data packet from the alert on lan asic. ? 64x16 1 mhz eeprom the alert on lan asic is designed to use a 64x16 1 mhz eeprom to configure the default settings upon reset and hard g2 transitions. if an eeprom is not present or contains an invalid checksum, the alert on lan asic defaults to its component default settings as defined in section section 4.0, configuration and status registers on page 17 . note : the alert on lan asic requires the use of an eeprom for its configuration settings; this is a separate eeprom from the 82558bs eeprom. ? environmental integrated circuit an environmental ic that is capable of monitoring voltage, temperature, and cover tamper can be used as part of the system management solution. however, only one input signal on the alert on lan asic exists (event_2). if voltage is out of specification, the alert on lan asic expects to receive an event on the event_2 signal. the alert on lan uses two other inputs, event_3 (bti temperature) and event_1 (cover tamper), to monitor these other events. this is required since the alert on lan asic does not have the ability to distinguish the difference between temperature and voltage events over one input signal. ? piix4 or equivalent the pci-to-isa/ide xcelerator (piix4) provides the smb master interface that enables the system bios and os to communicate with the alert on lan asic. piix4 also provides the pwr_good and pci_rst# signals that propagate to the alert on lan asic. note : the piix4 has the ability to force the system into a low power state without prior indication to software. this is the reason the alert on lan asic monitors pwr_good for a hard g2 transition. ? sticky latch (optional) sticky latches can are useful for detecting events that occur when the system is in a g3 state (completely off), such as cover tamper input. the latch can be battery-backed so that the alert on lan asic will become aware that an event occurred when it is powered-up. a sticky latch also provides the ability to be reset by driving the opposite polarity to the latch on the bidirectional pin, event_1, of the alert on lan asic. the event_1 pin of the alert on lan asic has the ability to clear a sticky latch. if this feature is enabled, it is executed by clearing the sta_ev1 bit in the event status register. the result is at least a 20 ms output
alert on lan* asic networking silicon 32 datasheet pulse of opposite polarity on the event_1 pin. an example sticky latch circuit is illustrated in figure 4 . note: this solution also prohibits the use of the asic cover tamper clear mechanism (the asic can be configured to output a 20 ms clear pulse). the environmental ic should clear the sticky latch. figure 4. sticky latch example 2m 2m 10k set sample/clear 5vsb

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